Hello I'm Benny

I am currently interning at Bosch for an 8 month co-op as an embedded systems engineer. Currently, my work is to implement system designs for transmitting and receiving data from inertial measurement units for velocity, acceleration and temperature.

To do this, I use the tool AMD Xilinx Vivado to create RTL designs through Verilog. Design for data TX/RX includes the usage of asynchronous FIFO to allow for clock domain crossings between the FTDI and FPGA board. Additionally, design also includes the usage of IP cores such as MIG DDR3 SDRAM to allow reading and writing requests to DDR3 Memory. I have created FSM to allow for reading and writing data for user logic to MIG DDR3 RAM. I also used IP cores such as clocking wizard to have 50MHz clock from ui_clock to provide 100 MHz clock for clock reference which would allow for proper calibration of the MIG to allow for the process of reading and writing data into X address to begin. I had to use ILA Debug core to have proper testing, writing test benches as well. I also had to properly go through the data sheet to properly setup XDC constraint file for implementation of the project.

A little about myself: I enjoy learning new concepts and understanding how things work and why they work — whether engineering or non-engineering. I really enjoy nature and have learned to appreciate the beauties it has to offer. I also enjoy playing and watching basketball, and I like learning how to cook new dishes.